PIC18LF66K80-I/PT【PDF 98/351 页】MCU PIC ECAN 64KB FLASH 64TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3841

94页 95页 96页 97页 [98页]99页 100页 101页 102页

2010-2012 Microchip Technology Inc.

DS39977F-page 187

PIC18F66K80 FAMILY

11.6

PORTE, TRISE and

LATE Registers

PORTE is a seven-bit-wide, bidirectional port. The

corresponding Data Direction and Output Latch registers

are TRISE and LATE.

All pins on PORTE are implemented with Schmitt

Trigger input buffers. Each pin is individually

configurable as an input or output.

Each of the PORTE pins has a weak internal pull-up. A

single control bit can turn off all the pull-ups. This is

performed by clearing bit, REPU (PADCFG1<6>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on any device Reset.

PORTE is also multiplexed with the Parallel Slave Port

address lines. RE1 and RE0 are multiplexed with the

Parallel Slave Port (PSP) control signals, WR and RD.

EXAMPLE 11-5:

INITIALIZING PORTE

Note:

PORTE is unavailable on 28-pin devices.

Note:

These pins are configured as digital inputs

on any device Reset.

CLRF

PORTE

; Initialize PORTE by

; clearing output

; data latches

CLRF

LATE

; Alternate method

; to clear output

; data latches

MOVLW

03h

; Value used to

; initialize data

; direction

MOVWF

TRISE

; Set RE<1:0> as inputs

; RE<7:2> as outputs

TABLE 11-9:

PORTE FUNCTIONS

Pin Name

Function

TRIS

Setting

I/O

I/O Type

Description

RE0/AN5/RD

RE0

DIG

LATE<0> data output.

PORTE<0> data input.

AN5

ANA

A/D Input Channel 5. Default input configuration on POR; does not

affect digital output.

DIG

Parallel Slave Port read strobe pin.

Parallel Slave Port read pin.

RE1/AN6/

C1OUT/WR

RE1

DIG

LATE<1> data output.

PORTE<1> data input.

AN6

ANA

A/D Input Channel 5. Default input configuration on POR; does not

affect digital output.

C1OUT

DIG

Comparator 1 output; takes priority over port data.

DIG

Parallel Slave Port write strobe pin.

Parallel Slave Port write pin.

RE2/AN7/

C2OUT/CS

RE2

DIG

LATE<2> data output.

PORTE<2> data input.

AN7

ANA

A/D Input Channel 7. Default input configuration on POR; does not

affect digital output.

C2OUT

DIG

Comparator 2 output; takes priority over port data.

Parallel Slave Port chip select.

RE3

PORT<3> data input.

RE4/CANRX

RE4(1)

DIG

LATE<4> data output.

PORTE<4> data input.

CANRX(1,2)

CAN bus RX.

Legend:

O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,

= Don’t care (TRIS bit does not affect port direction or is overridden for this option)

Note

These bits are unavailable for 40 and 44-pin devices (PIC18F4XK0).

This is the alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX

Configuration bit is cleared.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式